v_cvt_pk_f32_fp8 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_pk_f32_fp8

Convert from a packed 2-component FP8 float input to a packed single-precision float value and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1101110
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 110 in OP rebuilds 0x7E00DC00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 86, field layout), AMD CDNA 3 (opcode 86, field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 110
Identifier 0x7E00DC00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_FP8)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

SDWA encoding allows SRC0_SEL to control which word of S0 is converted. Only the WORD selects of SRC0_SEL are legal. If this instruction is not encoded in SDWA then WORD0 is implied.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = SDWA_SRC0_SEL[1 : 0] == WORD1.b2 ? S0[31 : 16] : S0[15 : 0]; D0[31 : 0].f32 = fp8_to_f32(tmp[7 : 0].fp8); D0[63 : 32].f32 = fp8_to_f32(tmp[15 : 8].fp8)

Example

v_cvt_pk_f32_fp8 v[2:3], v128.h

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1250_asm_vop3_from_vop1.s). Not from an AMD document, and not authored here.

Sources