v_cvt_norm_i16_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_norm_i16_f16

Convert from a half-precision float input to a signed normalized short and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1100011
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 99 in OP rebuilds 0x7E00C600, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 77, field layout), AMD CDNA 3 (opcode 77, field layout), AMD CDNA 2 (opcode 77, field layout), AMD CDNA 1 (opcode 77, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 99
Identifier 0x7E00C600

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 16-bit integral data. (OPR_VGPR, FMT_NUM_I16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP accuracy, supports rounding, exception flags and saturation, denormals are supported.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.i16 = f16_to_snorm(S0.f16)

Example

v_cvt_norm_i16_f16 v5.l, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources