AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 1 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| buffer_atomic_add_f64 | buffer_atomic_add_f64 | MUBUF | Add a double-precision float value in the data register to a location in a buffer surface. | ||
| buffer_atomic_add_u32 | buffer_atomic_add_u32 | MUBUF | gfx1100 | Add two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_add_u64 | buffer_atomic_add_u64 | MUBUF | gfx1100 | Add two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_and_b32 | buffer_atomic_and_b32 | MUBUF | gfx1100 | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_and_b64 | buffer_atomic_and_b64 | MUBUF | gfx1100 | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_cmpswap_b32 | buffer_atomic_cmpswap_b32 | MUBUF | gfx1100 | Compare two unsigned 32-bit integer values stored in the data comparison register and a location in a buffer surface. | |
| buffer_atomic_cmpswap_b64 | buffer_atomic_cmpswap_b64 | MUBUF | gfx1100 | Compare two unsigned 64-bit integer values stored in the data comparison register and a location in a buffer surface. | |
| buffer_atomic_cmpswap_f32 | buffer_atomic_cmpswap_f32 | MUBUF | gfx1100 | Compare two single-precision float values stored in the data comparison register and a location in a buffer surface. | |
| buffer_atomic_dec_u32 | buffer_atomic_dec_u32 | MUBUF | gfx1100 | Decrement an unsigned 32-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement… | |
| buffer_atomic_dec_u64 | buffer_atomic_dec_u64 | MUBUF | gfx1100 | Decrement an unsigned 64-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement… | |
| buffer_atomic_fmax_x2 | buffer_atomic_fmax_x2 | MUBUF | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. | ||
| buffer_atomic_fmin_x2 | buffer_atomic_fmin_x2 | MUBUF | Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. | ||
| buffer_atomic_inc_u32 | buffer_atomic_inc_u32 | MUBUF | gfx1100 | Increment an unsigned 32-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. | |
| buffer_atomic_inc_u64 | buffer_atomic_inc_u64 | MUBUF | gfx1100 | Increment an unsigned 64-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. | |
| buffer_atomic_max_f64 | buffer_atomic_max_f64 | MUBUF | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. | ||
| buffer_atomic_max_i32 | buffer_atomic_max_i32 | MUBUF | gfx1100 | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_max_i64 | buffer_atomic_max_i64 | MUBUF | gfx1100 | Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_max_num_f32 | buffer_atomic_max_num_f32 | MUBUF | gfx1100 | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_max_num_f64 | buffer_atomic_max_num_f64 | MUBUF | AMDGPU MUBUF vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_atomic_max_u32 | buffer_atomic_max_u32 | MUBUF | gfx1100 | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_max_u64 | buffer_atomic_max_u64 | MUBUF | gfx1100 | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_min_f64 | buffer_atomic_min_f64 | MUBUF | Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. | ||
| buffer_atomic_min_i32 | buffer_atomic_min_i32 | MUBUF | gfx1100 | Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_min_i64 | buffer_atomic_min_i64 | MUBUF | gfx1100 | Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_min_num_f32 | buffer_atomic_min_num_f32 | MUBUF | gfx1100 | Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_min_num_f64 | buffer_atomic_min_num_f64 | MUBUF | AMDGPU MUBUF vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_atomic_min_u32 | buffer_atomic_min_u32 | MUBUF | gfx1100 | Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_min_u64 | buffer_atomic_min_u64 | MUBUF | gfx1100 | Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_or_b32 | buffer_atomic_or_b32 | MUBUF | gfx1100 | Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_or_b64 | buffer_atomic_or_b64 | MUBUF | gfx1100 | Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_rsub | buffer_atomic_rsub | MUBUF | AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_atomic_rsub_x2 | buffer_atomic_rsub_x2 | MUBUF | AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_atomic_sub_clamp_u32 | buffer_atomic_sub_clamp_u32 | MUBUF | gfx1100 | Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero. | |
| buffer_atomic_sub_u32 | buffer_atomic_sub_u32 | MUBUF | gfx1100 | Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a buffer surface. | |
| buffer_atomic_sub_u64 | buffer_atomic_sub_u64 | MUBUF | gfx1100 | Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a buffer surface. | |
| buffer_atomic_swap_b32 | buffer_atomic_swap_b32 | MUBUF | gfx1100 | Swap an unsigned 32-bit integer value in the data register with a location in a buffer surface. | |
| buffer_atomic_swap_b64 | buffer_atomic_swap_b64 | MUBUF | gfx1100 | Swap an unsigned 64-bit integer value in the data register with a location in a buffer surface. | |
| buffer_atomic_xor_b32 | buffer_atomic_xor_b32 | MUBUF | gfx1100 | Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_atomic_xor_b64 | buffer_atomic_xor_b64 | MUBUF | gfx1100 | Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. | |
| buffer_gl0_inv | buffer_gl0_inv | MUBUF | gfx1100 | Write back and invalidate the shader L0. Returns ACK to shader. | |
| buffer_gl1_inv | buffer_gl1_inv | MUBUF | gfx1100 | Invalidate the GL1 cache only. Returns ACK to shader. | |
| buffer_inv | buffer_inv | MUBUF | Invalidate CU and/or L2 cache depending on sc0 and sc1 bits. Returns ACK to shader. | ||
| buffer_invl2 | buffer_invl2 | MUBUF | Invalidate L2 cache. Returns ACK to shader. | ||
| buffer_load_b128 | buffer_load_b128 | MUBUF | gfx1100 | Load 128 bits of data from a buffer surface into a vector register. | |
| buffer_load_b32 | buffer_load_b32 | MUBUF | gfx1100 | Load 32 bits of data from a buffer surface into a vector register. | |
| buffer_load_b64 | buffer_load_b64 | MUBUF | gfx1100 | Load 64 bits of data from a buffer surface into a vector register. | |
| buffer_load_b96 | buffer_load_b96 | MUBUF | gfx1100 | Load 96 bits of data from a buffer surface into a vector register. | |
| buffer_load_d16_b16 | buffer_load_d16_b16 | MUBUF | gfx1100 | Load 16 bits of unsigned data from a buffer surface and store the result into the low 16 bits of a 32-bit vector register. | |
| buffer_load_d16_format_x | buffer_load_d16_format_x | MUBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| buffer_load_d16_format_xy | buffer_load_d16_format_xy | MUBUF | gfx1100 | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| buffer_load_d16_format_xyz | buffer_load_d16_format_xyz | MUBUF | gfx1100 | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| buffer_load_d16_format_xyzw | buffer_load_d16_format_xyzw | MUBUF | gfx1100 | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| buffer_load_d16_hi_b16 | buffer_load_d16_hi_b16 | MUBUF | gfx1100 | Load 16 bits of unsigned data from a buffer surface and store the result into the high 16 bits of a 32-bit vector register. | |
| buffer_load_d16_hi_format_x | buffer_load_d16_hi_format_x | MUBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| buffer_load_d16_hi_i8 | buffer_load_d16_hi_i8 | MUBUF | gfx1100 | Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | |
| buffer_load_d16_hi_u8 | buffer_load_d16_hi_u8 | MUBUF | gfx1100 | Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | |
| buffer_load_d16_i8 | buffer_load_d16_i8 | MUBUF | gfx1100 | Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | |
| buffer_load_d16_u8 | buffer_load_d16_u8 | MUBUF | gfx1100 | Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | |
| buffer_load_dword | buffer_load_dword VDST, VADDR, SRSRC, offset | MUBUF | gfx942, gfx1100 | Vector Memory Unit | Load one 32-bit dword per lane through a buffer (raw/structured) resource descriptor. |
| buffer_load_i16 | buffer_load_i16 | MUBUF | gfx1100 | Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | |
| buffer_load_i8 | buffer_load_i8 | MUBUF | gfx1100 | Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | |
| buffer_load_u16 | buffer_load_u16 | MUBUF | gfx1100 | Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | |
| buffer_load_u8 | buffer_load_u8 | MUBUF | gfx1100 | Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | |
| buffer_store_b128 | buffer_store_b128 | MUBUF | gfx1100 | Store 128 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b16 | buffer_store_b16 | MUBUF | gfx1100 | Store 16 bits of data from a vector register into a buffer surface. | |
| buffer_store_b32 | buffer_store_b32 | MUBUF | gfx1100 | Store 32 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b64 | buffer_store_b64 | MUBUF | gfx1100 | Store 64 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b8 | buffer_store_b8 | MUBUF | gfx1100 | Store 8 bits of data from a vector register into a buffer surface. | |
| buffer_store_b96 | buffer_store_b96 | MUBUF | gfx1100 | Store 96 bits of data from vector input registers into a buffer surface. | |
| buffer_store_d16_format_x | buffer_store_d16_format_x | MUBUF | gfx1100 | Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | |
| buffer_store_d16_format_xy | buffer_store_d16_format_xy | MUBUF | gfx1100 | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_format_xyz | buffer_store_d16_format_xyz | MUBUF | gfx1100 | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_format_xyzw | buffer_store_d16_format_xyzw | MUBUF | gfx1100 | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_hi_b16 | buffer_store_d16_hi_b16 | MUBUF | gfx1100 | Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | |
| buffer_store_d16_hi_b8 | buffer_store_d16_hi_b8 | MUBUF | gfx1100 | Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | |
| buffer_store_d16_hi_format_x | buffer_store_d16_hi_format_x | MUBUF | gfx1100 | Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | |
| buffer_store_lds_dword | buffer_store_lds_dword | MUBUF | Store one DWORD from LDS memory to system memory without utilizing VGPRs. | ||
| buffer_wbinvl1_sc | buffer_wbinvl1_sc | MUBUF | AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_wbinvl1_vol | buffer_wbinvl1_vol | MUBUF | Write back and invalidate the shader L1 only for lines that are marked volatile. Returns ACK to shader. | ||
| buffer_wbl2 | buffer_wbl2 | MUBUF | Write back L2 cache. Returns ACK to shader. | ||
| cluster_load_async_to_lds_b128 | cluster_load_async_to_lds_b128 | FLAT | AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b32 | cluster_load_async_to_lds_b32 | FLAT | AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b64 | cluster_load_async_to_lds_b64 | FLAT | AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b8 | cluster_load_async_to_lds_b8 | FLAT | AMDGPU FLAT vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b128 | cluster_load_b128 | FLAT | AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b32 | cluster_load_b32 | FLAT | AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b64 | cluster_load_b64 | FLAT | AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_f32 | ds_add_f32 | DS | gfx1100 | Add two single-precision float values stored in the data register and a location in a data share. | |
| ds_add_f64 | ds_add_f64 | DS | Add a double-precision float value in the data register to a location in a data share. | ||
| ds_add_gs_reg_rtn | ds_add_gs_reg_rtn | DS | gfx1100 | Perform an atomic add to data in specific registers embedded in GDS rather than operating on GDS memory directly. | |
| ds_add_rtn_f32 | ds_add_rtn_f32 | DS | gfx1100 | Add two single-precision float values stored in the data register and a location in a data share. | |
| ds_add_rtn_f64 | ds_add_rtn_f64 | DS | Add a double-precision float value in the data register to a location in a data share. | ||
| ds_add_rtn_u32 | ds_add_rtn_u32 | DS | gfx1100 | Add two unsigned 32-bit integer values stored in the data register and a location in a data share. | |
| ds_add_rtn_u64 | ds_add_rtn_u64 | DS | gfx1100 | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_add_src2_f32 | ds_add_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_src2_u32 | ds_add_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_src2_u64 | ds_add_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_u32 | ds_add_u32 ADDR, DATA, offset | DS | gfx942, gfx1100 | LDS Unit | Atomically add a per-lane value to an LDS location. |
| ds_add_u64 | ds_add_u64 | DS | gfx1100 | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_b32 | ds_and_b32 | DS | gfx1100 | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗