AMDGPU / GFX Instructions GPU Native ISA AMD

2,442 instructions - showing 100 per page, page 1 of 25 - AMDGPU/GFX is AMD's native, low-level GPU instruction set family, assembled directly with no virtual intermediate layer. Supported instructions and their exact encodings vary by GFX compatibility target (e.g. gfx942, gfx1100). Scalar instructions execute once per wavefront on the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.

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Mnemonic ⇅ Syntax Format ⇅ GFX Targets Unit ⇅ Summary

Source

Instruction names, formats and GFX targets come from LLVM's AMDGPU backend. Operands, bit layouts and the instructions that backend's TableGen does not reach come from AMD's machine-readable ISA specification; descriptions and semantics from AMD's own manuals and that specification; examples from LLVM's assembler tests. Each instruction page cites the sources it uses; AMD's ROCm documentation hub is the architecture-level reference. AMD machine-readable ISA specification ↗ · AMD Instinct MI300 ISA manual ↗ · LLVM AMDGPU backend ↗ · ROCm documentation ↗