buffer_load_d16_i8 GPU Native ISA AMD Vector
BUFFER LOAD D16 I8 Buffer Memory
buffer_load_d16_i8
Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (MUBUF)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Buffer Memory
Reference
AMDGPU / GFX ISA
Example
buffer_load_d16_i8 v5, off, s[8:11], s3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project