buffer_gl0_inv GPU Native ISA AMD Vector
Buffer Memory
buffer_gl0_inv
Write back and invalidate the shader L0. Returns ACK to shader.
Encoding
Binary Layout (AMD RDNA 3.5)
SOFFSET
63:56
IDXEN
55
OFFEN
54
TFE
53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
00101011
25:18
unassigned
17:15
GLC
14
DLC
13
SLC
12
OFFSET
11:0
The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 43 in OP rebuilds 0x00000000E0AC0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD RDNA 3.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Buffer Memory
Reference
AMDGPU / GFX ISA
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.