buffer_load_b96 GPU Native ISA AMD Vector

Buffer Memory

buffer_load_b96

Load 96 bits of data from a buffer surface into a vector register.

Also written as buffer_load_dwordx3. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
00010110
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 22 in OP rebuilds 0x0000000000000000C4058000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_MUBUF, field layout), AMD RDNA 3 (encoding ENC_MUBUF, field layout). The same in AMD RDNA 4.

Format MUBUF
Width 96 bits
Opcode 22
Identifier 0x0000000000000000C4058000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Example

buffer_load_b96 v[5:7], off, s[8:11], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources