buffer_load_d16_hi_u8 GPU Native ISA AMD Vector

BUFFER LOAD D16 HI U8 Buffer Memory

buffer_load_d16_hi_u8

Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Example

buffer_load_d16_hi_u8 v5, off, s[8:11], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources