buffer_inv GPU Native ISA AMD Vector

Buffer Memory

buffer_inv

Invalidate CU and/or L2 cache depending on sc0 and sc1 bits. Returns ACK to shader.

Also written as buffer_invl2. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
0101001
24:18
NT
17
LDS
16
SC1
15
SC0
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 41 in OP rebuilds 0x00000000E0A40000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD CDNA 3.

Format MUBUF
Width 64 bits
Opcode 41
Identifier 0x00000000E0A40000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Sources