buffer_atomic_sub_clamp_u32 GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_sub_clamp_u32

Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero.

Also written as buffer_atomic_csub, buffer_atomic_csub_u32. AMD's machine-readable ISA specification lists these names for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
00110111
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 55 in OP rebuilds 0x0000000000000000C40DC000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 4.

Format MUBUF
Width 96 bits
Opcode 55
Identifier 0x0000000000000000C40DC000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.

Sources