buffer_atomic_csub_u32 GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_csub_u32

Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero.

Also written as buffer_atomic_csub, buffer_atomic_sub_clamp_u32. AMD's machine-readable ISA specification lists these names for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
SOFFSET
63:56
IDXEN
55
OFFEN
54
TFE
53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
00110111
25:18
unassigned
17:15
GLC
14
DLC
13
SLC
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 55 in OP rebuilds 0x00000000E0DC0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 3.

Format MUBUF
Width 64 bits
Opcode 55
Identifier 0x00000000E0DC0000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register, m0 or an inline constant. Data format: Value can be anything. (OPR_SREG_M0_INL, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MUBUF encoding (AMD RDNA 3.5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Subtract an unsigned 32-bit integer location in a buffer surface from a value in the data register and clamp the result to zero. Store the original value from buffer surface into a vector register iff the GLC bit is set.

Example

buffer_atomic_csub_u32 v5, off, s[8:11], s3 glc

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11_asm_mubuf.s). Not from an AMD document, and not authored here.

Sources