buffer_atomic_add_f64 GPU Native ISA AMD Vector
BUFFER ATOMIC ADD F64 Buffer Memory
buffer_atomic_add_f64
Add a double-precision float value in the data register to a location in a buffer surface.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (MUBUF)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Floating-point addition handles NAN/INF/denorm.
Related
More in Buffer Memory
Reference
AMDGPU / GFX ISA
Description
Add a double-precision float value in the data register to a location in a buffer surface. Store the original value from buffer surface into a vector register iff the SC0 bit is set.
Semantics
tmp = MEM[ADDR].f64;
MEM[ADDR].f64 += DATA.f64;
RETURN_DATA = tmp
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 472.