buffer_atomic_add_f32 GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_add_f32

Add two single-precision float values stored in the data register and a location in a buffer surface.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
01010110
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 86 in OP rebuilds 0x0000000000000000C4158000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_MUBUF, opcode 77, field layout), AMD CDNA 3 (encoding ENC_MUBUF, opcode 77, field layout), AMD CDNA 2 (encoding ENC_MUBUF, opcode 77, field layout), AMD CDNA 1 (encoding ENC_MUBUF, opcode 77, field layout), AMD RDNA 3.5 (encoding ENC_MUBUF, field layout), AMD RDNA 3 (encoding ENC_MUBUF, field layout). The same in AMD RDNA 4.

Format MUBUF
Width 96 bits
Opcode 86
Identifier 0x0000000000000000C4158000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Add two single-precision float values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.

Example

buffer_atomic_add_f32 v5, off, s[8:11], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11_asm_mubuf.s). Not from an AMD document, and not authored here.

Sources