buffer_atomic_fmin GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_fmin

Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface.

Also written as buffer_atomic_min_f32, buffer_atomic_min_num_f32. AMD's machine-readable ISA specification lists these names for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 128-bit buffer resource constant. (OPR_SREG_NONULL, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register, m0 or an inline constant. Data format: Value can be anything. (OPR_SREG_M0_INL, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MUBUF encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the GLC bit is set.

Example

buffer_atomic_fmin v0, off, s[0:3], s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (mubuf-gfx10.s). Not from an AMD document, and not authored here.

Sources