buffer_atomic_max_num_f64 GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_max_num_f64

AMDGPU MUBUF vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
01011100
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 92 in OP rebuilds 0x0000000000000000C4170000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. No other generation in the specification defines this instruction.

Format MUBUF
Width 96 bits
Opcode 92
Identifier 0x0000000000000000C4170000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Sources