buffer_atomic_max_i32 GPU Native ISA AMD Vector

BUFFER ATOMIC MAX I32 Buffer Memory

buffer_atomic_max_i32

Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.

Example

buffer_atomic_max_i32 v5, off, s[8:11], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources