buffer_atomic_min_f64 GPU Native ISA AMD Vector

Buffer Memory

buffer_atomic_min_f64

Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
1010000
24:18
NT
17
LDS
16
SC1
15
SC0
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 80 in OP rebuilds 0x00000000E1400000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 2 (field layout). The same in AMD CDNA 3.

Format MUBUF
Width 64 bits
Opcode 80
Identifier 0x00000000E1400000

Operands

  • VDATA
    Written. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. N/A Data format: Value can be anything. (OPR_SSRC_NOLIT, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MUBUF encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the SC0 bit is set.

Semantics

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32); tmp = MEM[addr].f64; src = DATA.f64; MEM[addr].f64 = src < tmp ? src : tmp; RETURN_DATA.f64 = tmp

Sources