buffer_atomic_min_f64 GPU Native ISA AMD Vector

BUFFER ATOMIC MIN F64 Buffer Memory

buffer_atomic_min_f64

Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the SC0 bit is set.

Semantics

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32); tmp = MEM[addr].f64; src = DATA.f64; MEM[addr].f64 = src < tmp ? src : tmp; RETURN_DATA.f64 = tmp

Sources