buffer_atomic_min_num_f32 GPU Native ISA AMD Vector
BUFFER ATOMIC MIN NUM F32 Buffer Memory
buffer_atomic_min_num_f32
Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (MUBUF)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Buffer Memory
Reference
AMDGPU / GFX ISA
Description
Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Update the buffer surface with the selected value. Store the original value from buffer surface into a vector register iff the temporal hint enables atomic return.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.