buffer_atomic_cmpswap_f32 GPU Native ISA AMD Vector

BUFFER ATOMIC CMPSWAP F32 Buffer Memory

buffer_atomic_cmpswap_f32

Compare two single-precision float values stored in the data comparison register and a location in a buffer surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Compare two single-precision float values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set.

Example

buffer_atomic_cmpswap_f32 v[5:6], off, s[8:11], s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources