buffer_load_dword GPU Native ISA AMD Vector

Buffer Memory

buffer_load_dword VDST, VADDR, SRSRC, offset

Load one 32-bit dword per lane through a buffer (raw/structured) resource descriptor.

Also written as buffer_load_b32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
0010100
24:18
NT
17
LDS
16
SC1
15
SC0
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 20 in OP rebuilds 0x00000000E0500000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD CDNA 3.

Format MUBUF
Width 64 bits
Opcode 20
Identifier 0x00000000E0500000
Execution Unit Vector Memory Unit
Register Classes VGPR, SGPR
Memory Segment buffer

Operands

  • VDST
    Destination VGPR
  • VADDR
    Per-lane offset (VGPR)
  • SRSRC
    Buffer resource descriptor (SGPR x4)
  • offset
    Immediate offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Global-Memory Load ↗
equivalent with restrictions
ld (PTX)

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from a buffer surface into a vector register.

Semantics

VDST[lane] = *(resource-relative address computed from SRSRC, VADDR[lane], offset) for each active lane; bounds-checked against the descriptor.

Example

buffer_load_dword  v2, v0, s[4:7], 0 offen   // v2 = buffer[s[4:7]](v0)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources