buffer_load_dword GPU Native ISA AMD Vector

BUFFER LOAD DWORD Buffer Memory

buffer_load_dword VDST, VADDR, SRSRC, offset

Load one 32-bit dword per lane through a buffer (raw/structured) resource descriptor.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MUBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MUBUF
Width 32 bits
Execution Unit Vector Memory Unit
Register Classes VGPR, SGPR
Memory Segment buffer

Operands

  • VDST
    Destination VGPR
  • VADDR
    Per-lane offset (VGPR)
  • SRSRC
    Buffer resource descriptor (SGPR x4)
  • offset
    Immediate offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Global-Memory Load ↗
equivalent with restrictions
ld (PTX)

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Load 32 bits of data from a buffer surface into a vector register.

Semantics

VDST[lane] = *(resource-relative address computed from SRSRC, VADDR[lane], offset) for each active lane; bounds-checked against the descriptor.

Example

buffer_load_dword  v2, v0, s[4:7], 0 offen   // v2 = buffer[s[4:7]](v0)

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources