AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 2 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| buffer_load_format_d16_hi_x | buffer_load_format_d16_hi_x | MUBUF | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| buffer_load_format_d16_x | buffer_load_format_d16_x | MUBUF | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| buffer_load_format_d16_xy | buffer_load_format_d16_xy | MUBUF | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| buffer_load_format_d16_xyz | buffer_load_format_d16_xyz | MUBUF | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| buffer_load_format_d16_xyzw | buffer_load_format_d16_xyzw | MUBUF | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| buffer_load_format_x | buffer_load_format_x | MUBUF | Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | ||
| buffer_load_format_xy | buffer_load_format_xy | MUBUF | Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | ||
| buffer_load_format_xyz | buffer_load_format_xyz | MUBUF | Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | ||
| buffer_load_format_xyzw | buffer_load_format_xyzw | MUBUF | Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | ||
| buffer_load_i16 | buffer_load_i16 | MUBUF | gfx1100 | Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | |
| buffer_load_i8 | buffer_load_i8 | MUBUF | gfx1100 | Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | |
| buffer_load_sbyte | buffer_load_sbyte | MUBUF | Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | ||
| buffer_load_sbyte_d16 | buffer_load_sbyte_d16 | MUBUF | Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| buffer_load_sbyte_d16_hi | buffer_load_sbyte_d16_hi | MUBUF | Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| buffer_load_short_d16 | buffer_load_short_d16 | MUBUF | Load 16 bits of unsigned data from a buffer surface and store the result into the low 16 bits of a 32-bit vector register. | ||
| buffer_load_short_d16_hi | buffer_load_short_d16_hi | MUBUF | Load 16 bits of unsigned data from a buffer surface and store the result into the high 16 bits of a 32-bit vector register. | ||
| buffer_load_sshort | buffer_load_sshort | MUBUF | Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. | ||
| buffer_load_u16 | buffer_load_u16 | MUBUF | gfx1100 | Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | |
| buffer_load_u8 | buffer_load_u8 | MUBUF | gfx1100 | Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | |
| buffer_load_ubyte | buffer_load_ubyte | MUBUF | Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | ||
| buffer_load_ubyte_d16 | buffer_load_ubyte_d16 | MUBUF | Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| buffer_load_ubyte_d16_hi | buffer_load_ubyte_d16_hi | MUBUF | Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| buffer_load_ushort | buffer_load_ushort | MUBUF | Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. | ||
| buffer_store_b128 | buffer_store_b128 | MUBUF | gfx1100 | Store 128 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b16 | buffer_store_b16 | MUBUF | gfx1100 | Store 16 bits of data from a vector register into a buffer surface. | |
| buffer_store_b32 | buffer_store_b32 | MUBUF | gfx1100 | Store 32 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b64 | buffer_store_b64 | MUBUF | gfx1100 | Store 64 bits of data from vector input registers into a buffer surface. | |
| buffer_store_b8 | buffer_store_b8 | MUBUF | gfx1100 | Store 8 bits of data from a vector register into a buffer surface. | |
| buffer_store_b96 | buffer_store_b96 | MUBUF | gfx1100 | Store 96 bits of data from vector input registers into a buffer surface. | |
| buffer_store_byte | buffer_store_byte | MUBUF | Store 8 bits of data from a vector register into a buffer surface. | ||
| buffer_store_byte_d16_hi | buffer_store_byte_d16_hi | MUBUF | Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | ||
| buffer_store_d16_format_x | buffer_store_d16_format_x | MUBUF | gfx1100 | Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | |
| buffer_store_d16_format_xy | buffer_store_d16_format_xy | MUBUF | gfx1100 | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_format_xyz | buffer_store_d16_format_xyz | MUBUF | gfx1100 | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_format_xyzw | buffer_store_d16_format_xyzw | MUBUF | gfx1100 | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| buffer_store_d16_hi_b16 | buffer_store_d16_hi_b16 | MUBUF | gfx1100 | Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | |
| buffer_store_d16_hi_b8 | buffer_store_d16_hi_b8 | MUBUF | gfx1100 | Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | |
| buffer_store_d16_hi_format_x | buffer_store_d16_hi_format_x | MUBUF | gfx1100 | Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | |
| buffer_store_dword | buffer_store_dword | MUBUF | Store 32 bits of data from vector input registers into a buffer surface. | ||
| buffer_store_dwordx2 | buffer_store_dwordx2 | MUBUF | Store 64 bits of data from vector input registers into a buffer surface. | ||
| buffer_store_dwordx3 | buffer_store_dwordx3 | MUBUF | Store 96 bits of data from vector input registers into a buffer surface. | ||
| buffer_store_dwordx4 | buffer_store_dwordx4 | MUBUF | Store 128 bits of data from vector input registers into a buffer surface. | ||
| buffer_store_format_d16_hi_x | buffer_store_format_d16_hi_x | MUBUF | Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | ||
| buffer_store_format_d16_x | buffer_store_format_d16_x | MUBUF | Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer… | ||
| buffer_store_format_d16_xy | buffer_store_format_d16_xy | MUBUF | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_d16_xyz | buffer_store_format_d16_xyz | MUBUF | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_d16_xyzw | buffer_store_format_d16_xyzw | MUBUF | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_x | buffer_store_format_x | MUBUF | Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_xy | buffer_store_format_xy | MUBUF | Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_xyz | buffer_store_format_xyz | MUBUF | Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | ||
| buffer_store_format_xyzw | buffer_store_format_xyzw | MUBUF | Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | ||
| buffer_store_lds_dword | buffer_store_lds_dword | MUBUF | Store one DWORD from LDS memory to system memory without utilizing VGPRs. | ||
| buffer_store_short | buffer_store_short | MUBUF | Store 16 bits of data from a vector register into a buffer surface. | ||
| buffer_store_short_d16_hi | buffer_store_short_d16_hi | MUBUF | Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. | ||
| buffer_wbinvl1 | buffer_wbinvl1 | MUBUF | Write back and invalidate the shader L1. Returns ACK to shader. | ||
| buffer_wbinvl1_sc | buffer_wbinvl1_sc | MUBUF | AMDGPU MUBUF vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| buffer_wbinvl1_vol | buffer_wbinvl1_vol | MUBUF | Write back and invalidate the shader L1 only for lines that are marked volatile. Returns ACK to shader. | ||
| buffer_wbl2 | buffer_wbl2 | MUBUF | Write back L2 cache. Returns ACK to shader. | ||
| cluster_load_async_to_lds_b128 | cluster_load_async_to_lds_b128 | FLAT | AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b32 | cluster_load_async_to_lds_b32 | FLAT | AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b64 | cluster_load_async_to_lds_b64 | FLAT | AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_async_to_lds_b8 | cluster_load_async_to_lds_b8 | FLAT | AMDGPU FLAT vector instruction operating on b8 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b128 | cluster_load_b128 | FLAT | AMDGPU FLAT vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b32 | cluster_load_b32 | FLAT | AMDGPU FLAT vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| cluster_load_b64 | cluster_load_b64 | FLAT | AMDGPU FLAT vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_f32 | ds_add_f32 | DS | gfx1100 | Add two single-precision float values stored in the data register and a location in a data share. | |
| ds_add_f64 | ds_add_f64 | DS | Add a double-precision float value in the data register to a location in a data share. | ||
| ds_add_gs_reg_rtn | ds_add_gs_reg_rtn | DS | gfx1100 | Perform an atomic add to data in specific registers embedded in GDS rather than operating on GDS memory directly. | |
| ds_add_rtn_f32 | ds_add_rtn_f32 | DS | gfx1100 | Add two single-precision float values stored in the data register and a location in a data share. | |
| ds_add_rtn_f64 | ds_add_rtn_f64 | DS | Add a double-precision float value in the data register to a location in a data share. | ||
| ds_add_rtn_u32 | ds_add_rtn_u32 | DS | gfx1100 | Add two unsigned 32-bit integer values stored in the data register and a location in a data share. | |
| ds_add_rtn_u64 | ds_add_rtn_u64 | DS | gfx1100 | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_add_src2_f32 | ds_add_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_src2_u32 | ds_add_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_src2_u64 | ds_add_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_add_u32 | ds_add_u32 ADDR, DATA, offset | DS | gfx942, gfx1100 | LDS Unit | Atomically add a per-lane value to an LDS location. |
| ds_add_u64 | ds_add_u64 | DS | gfx1100 | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_b32 | ds_and_b32 | DS | gfx1100 | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. | |
| ds_and_b64 | ds_and_b64 | DS | gfx1100 | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_rtn_b32 | ds_and_rtn_b32 | DS | gfx1100 | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. | |
| ds_and_rtn_b64 | ds_and_rtn_b64 | DS | gfx1100 | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_src2_b32 | ds_and_src2_b32 | DS | AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_and_src2_b64 | ds_and_src2_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_append | ds_append | DS | gfx1100 | Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. | |
| ds_atomic_async_barrier_arrive_b64 | ds_atomic_async_barrier_arrive_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_atomic_barrier_arrive_rtn_b64 | ds_atomic_barrier_arrive_rtn_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_bpermute_b32 | ds_bpermute_b32 | DS | gfx1100 | Backward permute. | |
| ds_bpermute_fi_b32 | ds_bpermute_fi_b32 | DS | Backward permute and fetch data for invalid lanes. | ||
| ds_bvh_stack_push4_pop1_rtn_b32 | ds_bvh_stack_push4_pop1_rtn_b32 | DS | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. | ||
| ds_bvh_stack_push8_pop1_rtn_b32 | ds_bvh_stack_push8_pop1_rtn_b32 | DS | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. | ||
| ds_bvh_stack_push8_pop2_rtn_b64 | ds_bvh_stack_push8_pop2_rtn_b64 | DS | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. | ||
| ds_bvh_stack_rtn_b32 | ds_bvh_stack_rtn_b32 | DS | gfx1100 | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. | |
| ds_cmpst_b32 | ds_cmpst_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_b64 | ds_cmpst_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_f32 | ds_cmpst_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_f64 | ds_cmpst_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_b32 | ds_cmpst_rtn_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_b64 | ds_cmpst_rtn_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_f32 | ds_cmpst_rtn_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_f64 | ds_cmpst_rtn_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗