AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 2 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| ds_and_b64 | ds_and_b64 | DS | gfx1100 | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_rtn_b32 | ds_and_rtn_b32 | DS | gfx1100 | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. | |
| ds_and_rtn_b64 | ds_and_rtn_b64 | DS | gfx1100 | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. | |
| ds_and_src2_b32 | ds_and_src2_b32 | DS | AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_and_src2_b64 | ds_and_src2_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_append | ds_append | DS | gfx1100 | Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. | |
| ds_atomic_async_barrier_arrive_b64 | ds_atomic_async_barrier_arrive_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_atomic_barrier_arrive_rtn_b64 | ds_atomic_barrier_arrive_rtn_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_bpermute_b32 | ds_bpermute_b32 | DS | gfx1100 | Backward permute. | |
| ds_bpermute_fi_b32 | ds_bpermute_fi_b32 | DS | Backward permute and fetch data for invalid lanes. | ||
| ds_bvh_stack_rtn_b32 | ds_bvh_stack_rtn_b32 | DS | gfx1100 | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. | |
| ds_cmpst_b32 | ds_cmpst_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_b64 | ds_cmpst_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_f32 | ds_cmpst_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_f64 | ds_cmpst_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_b32 | ds_cmpst_rtn_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_b64 | ds_cmpst_rtn_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_f32 | ds_cmpst_rtn_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpst_rtn_f64 | ds_cmpst_rtn_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | ||
| ds_cmpstore_b32 | ds_cmpstore_b32 | DS | gfx1100 | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_b64 | ds_cmpstore_b64 | DS | gfx1100 | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_f32 | ds_cmpstore_f32 | DS | gfx1100 | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_f64 | ds_cmpstore_f64 | DS | gfx1100 | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_rtn_b32 | ds_cmpstore_rtn_b32 | DS | gfx1100 | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_rtn_b64 | ds_cmpstore_rtn_b64 | DS | gfx1100 | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_rtn_f32 | ds_cmpstore_rtn_f32 | DS | gfx1100 | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cmpstore_rtn_f64 | ds_cmpstore_rtn_f64 | DS | gfx1100 | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… | |
| ds_cond_sub_rtn_u32 | ds_cond_sub_rtn_u32 | DS | Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to… | ||
| ds_cond_sub_u32 | ds_cond_sub_u32 | DS | Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to… | ||
| ds_condxchg32_rtn_b64 | ds_condxchg32_rtn_b64 | DS | gfx1100 | Perform 2 conditional write exchanges, where each conditional write exchange writes a 32 bit value from a data register to a location in data share… | |
| ds_consume | ds_consume | DS | gfx1100 | Subtract (count_bits(exec_mask)) from the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. | |
| ds_dec_rtn_u32 | ds_dec_rtn_u32 | DS | gfx1100 | Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… | |
| ds_dec_rtn_u64 | ds_dec_rtn_u64 | DS | gfx1100 | Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… | |
| ds_dec_src2_u32 | ds_dec_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_dec_src2_u64 | ds_dec_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_dec_u32 | ds_dec_u32 | DS | gfx1100 | Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… | |
| ds_dec_u64 | ds_dec_u64 | DS | gfx1100 | Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… | |
| ds_direct_load | ds_direct_load | DSDIR | Read a single 32-bit value from LDS to all lanes. | ||
| ds_gws_barrier | ds_gws_barrier | DS | gfx1100 | GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied. | |
| ds_gws_init | ds_gws_init | DS | gfx1100 | GDS Only: Initialize a barrier or semaphore resource. | |
| ds_gws_sema_br | ds_gws_sema_br | DS | gfx1100 | GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a… | |
| ds_gws_sema_p | ds_gws_sema_p | DS | gfx1100 | GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the… | |
| ds_gws_sema_release_all | ds_gws_sema_release_all | DS | gfx1100 | GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore. | |
| ds_gws_sema_v | ds_gws_sema_v | DS | gfx1100 | GDS Only: The GWS resource indicated processes this opcode by updating the counter and labeling the resource as a semaphore. | |
| ds_inc_rtn_u32 | ds_inc_rtn_u32 | DS | gfx1100 | Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. | |
| ds_inc_rtn_u64 | ds_inc_rtn_u64 | DS | gfx1100 | Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. | |
| ds_inc_src2_u32 | ds_inc_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_inc_src2_u64 | ds_inc_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_inc_u32 | ds_inc_u32 | DS | gfx1100 | Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. | |
| ds_inc_u64 | ds_inc_u64 | DS | gfx1100 | Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. | |
| ds_load_2addr_b32 | ds_load_2addr_b32 | DS | gfx1100 | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… | |
| ds_load_2addr_b64 | ds_load_2addr_b64 | DS | gfx1100 | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… | |
| ds_load_2addr_stride64_b32 | ds_load_2addr_stride64_b32 | DS | gfx1100 | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… | |
| ds_load_2addr_stride64_b64 | ds_load_2addr_stride64_b64 | DS | gfx1100 | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… | |
| ds_load_addtid_b32 | ds_load_addtid_b32 | DS | gfx1100 | Load 32 bits of data from a data share into a vector register. | |
| ds_load_b128 | ds_load_b128 | DS | gfx1100 | Load 128 bits of data from a data share into a vector register. | |
| ds_load_b32 | ds_load_b32 | DS | gfx1100 | Load 32 bits of data from a data share into a vector register. | |
| ds_load_b64 | ds_load_b64 | DS | gfx1100 | Load 64 bits of data from a data share into a vector register. | |
| ds_load_b96 | ds_load_b96 | DS | gfx1100 | Load 96 bits of data from a data share into a vector register. | |
| ds_load_i16 | ds_load_i16 | DS | gfx1100 | Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. | |
| ds_load_i8 | ds_load_i8 | DS | gfx1100 | Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. | |
| ds_load_i8_d16 | ds_load_i8_d16 | DS | gfx1100 | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register. | |
| ds_load_i8_d16_hi | ds_load_i8_d16_hi | DS | gfx1100 | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register. | |
| ds_load_tr16_b128 | ds_load_tr16_b128 | DS | AMDGPU DS vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_load_tr4_b64 | ds_load_tr4_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_load_tr6_b96 | ds_load_tr6_b96 | DS | AMDGPU DS vector instruction operating on b96 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_load_tr8_b64 | ds_load_tr8_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_load_u16 | ds_load_u16 | DS | gfx1100 | Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. | |
| ds_load_u16_d16 | ds_load_u16_d16 | DS | gfx1100 | Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register. | |
| ds_load_u16_d16_hi | ds_load_u16_d16_hi | DS | gfx1100 | Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register. | |
| ds_load_u8 | ds_load_u8 | DS | gfx1100 | Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. | |
| ds_load_u8_d16 | ds_load_u8_d16 | DS | gfx1100 | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register. | |
| ds_load_u8_d16_hi | ds_load_u8_d16_hi | DS | gfx1100 | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register. | |
| ds_max_f32 | ds_max_f32 | DS | gfx1100 | Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_f64 | ds_max_f64 | DS | gfx1100 | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_i32 | ds_max_i32 | DS | gfx1100 | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_i64 | ds_max_i64 | DS | gfx1100 | Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_num_f32 | ds_max_num_f32 | DS | gfx1100 | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_num_f64 | ds_max_num_f64 | DS | gfx1100 | Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_num_rtn_f32 | ds_max_num_rtn_f32 | DS | gfx1100 | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_num_rtn_f64 | ds_max_num_rtn_f64 | DS | gfx1100 | Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_f32 | ds_max_rtn_f32 | DS | gfx1100 | Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_f64 | ds_max_rtn_f64 | DS | gfx1100 | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_i32 | ds_max_rtn_i32 | DS | gfx1100 | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_i64 | ds_max_rtn_i64 | DS | gfx1100 | Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_u32 | ds_max_rtn_u32 | DS | gfx1100 | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_rtn_u64 | ds_max_rtn_u64 | DS | gfx1100 | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_src2_f32 | ds_max_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_src2_f64 | ds_max_src2_f64 | DS | AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_src2_i32 | ds_max_src2_i32 | DS | AMDGPU DS vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_src2_i64 | ds_max_src2_i64 | DS | AMDGPU DS vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_src2_u32 | ds_max_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_src2_u64 | ds_max_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| ds_max_u32 | ds_max_u32 | DS | gfx1100 | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_max_u64 | ds_max_u64 | DS | gfx1100 | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_min_f32 | ds_min_f32 | DS | gfx1100 | Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_min_f64 | ds_min_f64 | DS | gfx1100 | Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. | |
| ds_min_i32 | ds_min_i32 | DS | gfx1100 | Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_min_i64 | ds_min_i64 | DS | gfx1100 | Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. | |
| ds_min_num_f32 | ds_min_num_f32 | DS | gfx1100 | Select the IEEE minimumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗