buffer_store_format_x GPU Native ISA AMD Vector

Buffer Memory

buffer_store_format_x

Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
0000100
24:18
NT
17
LDS
16
SC1
15
SC0
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 4 in OP rebuilds 0x00000000E0100000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 4 (encoding ENC_VBUFFER, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD CDNA 3.

Format MUBUF
Width 64 bits
Opcode 4
Identifier 0x00000000E0100000

Operands

  • VDATA
    Read. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_TYPED)
  • SOFFSET
    Read. N/A Data format: Value can be anything. (OPR_SSRC_NOLIT, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MUBUF encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

Example

buffer_store_format_x v1, off, s[12:15], s4

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_mubuf.s). Not from an AMD document, and not authored here.

Sources