tbuffer_load_d16_format_xyz GPU Native ISA AMD Vector

Buffer Memory

tbuffer_load_d16_format_xyz

Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Also written as tbuffer_load_format_d16_xyz. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 4)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
10001010
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 138 in OP rebuilds 0x0000000000000000C4228000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_MTBUF, opcode 10, field layout), AMD RDNA 3 (encoding ENC_MTBUF, opcode 10, field layout).

Format MTBUF
Width 96 bits
Opcode 138
Identifier 0x0000000000000000C4228000

Operands

  • VDATA
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_TYPED)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD RDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

Example

tbuffer_load_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:13 offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources