tbuffer_store_d16_format_xyz GPU Native ISA AMD Vector

TBUFFER STORE D16 FORMAT XYZ Buffer Memory

tbuffer_store_d16_format_xyz

Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MTBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MTBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

Example

tbuffer_store_d16_format_xyz v[4:5], off, ttmp[4:7], 61, format:53 offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources