tbuffer_store_format_x GPU Native ISA AMD Vector
TBUFFER STORE FORMAT X Buffer Memory
tbuffer_store_format_x
Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (MTBUF)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Buffer Memory
Reference
AMDGPU / GFX ISA
Description
Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.
Semantics
addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32);
MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32);
// Mem access size depends on format
Example
tbuffer_store_format_x v255, off, s[8:11], s3, format:61 offset:4095A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 478. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project