tbuffer_store_format_xyz GPU Native ISA AMD Vector

TBUFFER STORE FORMAT XYZ Buffer Memory

tbuffer_store_format_xyz

Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MTBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MTBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

Semantics

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32); MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32); // Mem access size depends on format MEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32); MEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32)

Example

tbuffer_store_format_xyz v[4:6], off, s[8:11], s3, format:[BUF_FMT_32_FLOAT] offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources