tbuffer_load_format_xyz GPU Native ISA AMD Vector

TBUFFER LOAD FORMAT XYZ Buffer Memory

tbuffer_load_format_xyz

Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MTBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MTBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

Semantics

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32); VDATA[31 : 0].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetX()]); // Mem access size depends on format VDATA[63 : 32].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetY()]); VDATA[95 : 64].b32 = ConvertFromFormat(MEM[addr + ChannelOffsetZ()])

Example

tbuffer_load_format_xyz v[4:6], off, ttmp[4:7], 61, format:33 offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources