tbuffer_store_format_xyzw GPU Native ISA AMD Vector

Buffer Memory

tbuffer_store_format_xyzw

Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface.

Encoding

Binary Layout (AMD CDNA 4)
SOFFSET
63:56
ACC
55
NT
54
SC1
53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111010
31:26
NFMT
25:23
DFMT
22:19
0111
18:15
SC0
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MTBUF layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 7 in OP rebuilds 0x00000000E8038000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 2 (field layout), AMD CDNA 1 (field layout), AMD RDNA 4 (encoding ENC_VBUFFER, opcode 135, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (layout not verifiable), AMD RDNA 1 (layout not verifiable). The same in AMD CDNA 3.

Format MTBUF
Width 64 bits
Opcode 7
Identifier 0x00000000E8038000

Operands

  • VDATA
    Read. N/A Data format: Value can be anything. (OPR_VGPR_OR_ACCVGPR, FMT_ANY)
  • VADDR
    Read. N/A Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • SRSRC
    Read. N/A Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_TYPED)
  • SOFFSET
    Read. N/A Data format: Value can be anything. (OPR_SSRC_NOLIT, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MTBUF encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor.

Semantics

addr = CalcBufferAddr(VADDR.b32, SRSRC.b32, SOFFSET.b32, OFFSET.b32); MEM[addr + ChannelOffsetX()] = ConvertToFormat(VDATA[31 : 0].b32); // Mem access size depends on format MEM[addr + ChannelOffsetY()] = ConvertToFormat(VDATA[63 : 32].b32); MEM[addr + ChannelOffsetZ()] = ConvertToFormat(VDATA[95 : 64].b32); MEM[addr + ChannelOffsetW()] = ConvertToFormat(VDATA[127 : 96].b32)

Example

tbuffer_store_format_xyzw v[4:7], off, s[8:11], 0, format:[BUF_FMT_8_8_8_8_UNORM] offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources