tbuffer_load_d16_format_xyzw GPU Native ISA AMD Vector

TBUFFER LOAD D16 FORMAT XYZW Buffer Memory

tbuffer_load_d16_format_xyzw

Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (MTBUF) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format MTBUF
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Description

Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor.

Example

tbuffer_load_d16_format_xyzw v[4:5], off, ttmp[4:7], 61, format:18 offset:4095

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources