buffer_wbinvl1 GPU Native ISA AMD Vector

Buffer Memory

buffer_wbinvl1

Write back and invalidate the shader L1. Returns ACK to shader.

Encoding

Binary Layout (AMD CDNA 2)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
0111110
24:18
SLC
17
LDS
16
SCC
15
GLC
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 2). Opcode 62 in OP rebuilds 0x00000000E0F80000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 1 (field layout).

Format MUBUF
Width 64 bits
Opcode 62
Identifier 0x00000000E0F80000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Sources