buffer_store_lds_dword GPU Native ISA AMD Vector

Buffer Memory

buffer_store_lds_dword

Store one DWORD from LDS memory to system memory without utilizing VGPRs.

Encoding

Binary Layout (AMD CDNA 2)
SOFFSET
63:56
ACC
55
unassigned
54:53
SRSRC
52:48
VDATA
47:40
VADDR
39:32
111000
31:26
unassigned
25
0111101
24:18
SLC
17
LDS
16
SCC
15
GLC
14
IDXEN
13
OFFEN
12
OFFSET
11:0
 

The ENC_MUBUF layout from AMD's machine-readable ISA specification (AMD CDNA 2). Opcode 61 in OP rebuilds 0x00000000E0F40000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 1 (field layout).

Format MUBUF
Width 64 bits
Opcode 61
Identifier 0x00000000E0F40000

Operands

  • SRSRC
    Read. N/A Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. N/A Data format: Value can be anything. (OPR_SSRC_NOLIT, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_MUBUF encoding (AMD CDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Example

buffer_store_lds_dword s[4:7], s0 lds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_mubuf.s). Not from an AMD document, and not authored here.

Sources