buffer_store_b32 GPU Native ISA AMD Vector

Buffer Memory

buffer_store_b32

Store 32 bits of data from vector input registers into a buffer surface.

Also written as buffer_store_dword. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
IOFFSET
95:72
VADDR
71:64
IDXEN
63
OFFEN
62
FORMAT
61:55
TH
54:52
SCOPE
51:50
RSRC
49:41
unassigned
40
VDATA
39:32
110001
31:26
unassigned
25:23
TFE
22
00011010
21:14
unassigned
13:8
NV
7
SOFFSET
6:0
 

The ENC_VBUFFER layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 26 in OP rebuilds 0x0000000000000000C4068000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_MUBUF, field layout), AMD RDNA 3 (encoding ENC_MUBUF, field layout). The same in AMD RDNA 4.

Format MUBUF
Width 96 bits
Opcode 26
Identifier 0x0000000000000000C4068000

Operands

  • VDATA
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • VADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Value can be anything. (OPR_VGPR, FMT_ANY)
  • RSRC
    Read. Any scalar GPR operand including VCC and NULL. Data format: 128-bit buffer resource constant. (OPR_SREG, FMT_RSRC_SCRATCH)
  • SOFFSET
    Read. Vector memory operand that may be a scalar register or m0. Data format: Value can be anything. (OPR_SREG_M0, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VBUFFER encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Buffer Memory

Reference

AMDGPU / GFX ISA

Example

buffer_store_b32 v1, off, s[12:15], s4

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources