ds_add_rtn_f64 GPU Native ISA AMD Vector

LDS / Data Share

ds_add_rtn_f64

Add a double-precision float value in the data register to a location in a data share.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
01110100
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 116 in OP rebuilds 0x00000000D9D00000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_DS, opcode 124, field layout), AMD CDNA 3 (encoding ENC_DS, opcode 124, field layout), AMD CDNA 2 (encoding ENC_DS, opcode 124, field layout).

Format DS
Width 64 bits
Opcode 116
Identifier 0x00000000D9D00000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Floating-point addition handles NAN/INF/denorm.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Add a double-precision float value in the data register to a location in a data share. Store the original value from data share into a vector register.

Semantics

tmp = MEM[ADDR].f64; MEM[ADDR].f64 += DATA.f64; RETURN_DATA = tmp

Sources