ds_cmpst_rtn_f64 GPU Native ISA AMD Vector
DS CMPST RTN F64 LDS / Data Share
ds_cmpst_rtn_f64
Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.
Semantics
addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].f64;
src = DATA2.f64;
cmp = DATA.f64;
MEM[addr].f64 = tmp == cmp ? src : tmp;
RETURN_DATA.f64 = tmp
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 450.