ds_gws_sema_br GPU Native ISA AMD Vector

LDS / Data Share

ds_gws_sema_br

GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a…

Encoding

Binary Layout (AMD CDNA 3)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
10011011
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 3). Opcode 155 in OP rebuilds 0x00000000D9360000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 3.5 (opcode 27, field layout), AMD RDNA 3 (opcode 27, field layout), AMD RDNA 2 (opcode 27, field layout), AMD RDNA 1 (opcode 27, field layout). The same in AMD CDNA 2.

Format DS
Width 64 bits
Opcode 155
Identifier 0x00000000D9360000

Operands

  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 3).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a semaphore.

Semantics

//Determine the GWS resource to work on rid[5:0] = gds_base[5:0] + offset0[5:0]; index = find first valid (vector mask) count = DATA[thread: index]; //Add count to the resource state counter state.counter[rid] += count; state.type = SEMAPHORE; return rd_done; //release calling wave This action releases count number of waves, promptly if queued, or as they arrive from the noted resource. CAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware treats this instruction as a 64 bit read.

Example

ds_gws_sema_br v1 gds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources