ds_gws_init GPU Native ISA AMD Vector
DS GWS INIT LDS / Data Share
ds_gws_init
GDS Only: Initialize a barrier or semaphore resource.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Semantics
// Determine the GWS resource to work on
rid[5:0] = gds_base[5:0] + offset0[5:0];
// Get the value to use in init
index = find_first_valid(vector mask)
value = DATA[thread: index]
// Set the state of the resource
state.counter[rid] = lsb(value); //limit #waves
state.flag[rid] = 0;
return rd_done; //release calling wave
CAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware
treats this instruction as a 64 bit read.
Example
ds_gws_init v1 gdsA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 453. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project