ds_gws_sema_p GPU Native ISA AMD Vector
DS GWS SEMA P LDS / Data Share
ds_gws_sema_p
GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the resource as a semaphore.
Semantics
//Determine the GWS resource to work on
rid[5:0] = gds_base[5:0] + offset0[5:0];
state.type = SEMAPHORE;
ENQUEUE until(state[rid].counter > 0)
state[rid].counter -= 1;
return rd_done;
Example
ds_gws_sema_p gdsA real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 454. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project