LDS / Data Share Instructions
230 AMDGPU instructions in this category - showing 100 per page, page 1 of 3 - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ds_add_f32 | ds_add_f32 | DS | Add two single-precision float values stored in the data register and a location in a data share. |
| ds_add_f64 | ds_add_f64 | DS | Add a double-precision float value in the data register to a location in a data share. |
| ds_add_gs_reg_rtn | ds_add_gs_reg_rtn | DS | Perform an atomic add to data in specific registers embedded in GDS rather than operating on GDS memory directly. |
| ds_add_rtn_f32 | ds_add_rtn_f32 | DS | Add two single-precision float values stored in the data register and a location in a data share. |
| ds_add_rtn_f64 | ds_add_rtn_f64 | DS | Add a double-precision float value in the data register to a location in a data share. |
| ds_add_rtn_u32 | ds_add_rtn_u32 | DS | Add two unsigned 32-bit integer values stored in the data register and a location in a data share. |
| ds_add_rtn_u64 | ds_add_rtn_u64 | DS | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_add_src2_f32 | ds_add_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_add_src2_u32 | ds_add_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_add_src2_u64 | ds_add_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_add_u64 | ds_add_u64 | DS | Add two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_and_b32 | ds_and_b32 | DS | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. |
| ds_and_b64 | ds_and_b64 | DS | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_and_rtn_b32 | ds_and_rtn_b32 | DS | Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. |
| ds_and_rtn_b64 | ds_and_rtn_b64 | DS | Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. |
| ds_and_src2_b32 | ds_and_src2_b32 | DS | AMDGPU DS vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_and_src2_b64 | ds_and_src2_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_append | ds_append | DS | Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. |
| ds_atomic_async_barrier_arrive_b64 | ds_atomic_async_barrier_arrive_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_atomic_barrier_arrive_rtn_b64 | ds_atomic_barrier_arrive_rtn_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_bpermute_b32 | ds_bpermute_b32 | DS | Backward permute. |
| ds_bpermute_fi_b32 | ds_bpermute_fi_b32 | DS | Backward permute and fetch data for invalid lanes. |
| ds_bvh_stack_rtn_b32 | ds_bvh_stack_rtn_b32 | DS | Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. |
| ds_cmpst_b32 | ds_cmpst_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_b64 | ds_cmpst_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_f32 | ds_cmpst_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_f64 | ds_cmpst_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_rtn_b32 | ds_cmpst_rtn_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_rtn_b64 | ds_cmpst_rtn_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_rtn_f32 | ds_cmpst_rtn_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpst_rtn_f64 | ds_cmpst_rtn_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_b32 | ds_cmpstore_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_b64 | ds_cmpstore_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_f32 | ds_cmpstore_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_f64 | ds_cmpstore_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_rtn_b32 | ds_cmpstore_rtn_b32 | DS | Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_rtn_b64 | ds_cmpstore_rtn_b64 | DS | Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_rtn_f32 | ds_cmpstore_rtn_f32 | DS | Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cmpstore_rtn_f64 | ds_cmpstore_rtn_f64 | DS | Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value… |
| ds_cond_sub_rtn_u32 | ds_cond_sub_rtn_u32 | DS | Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to… |
| ds_cond_sub_u32 | ds_cond_sub_u32 | DS | Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to… |
| ds_condxchg32_rtn_b64 | ds_condxchg32_rtn_b64 | DS | Perform 2 conditional write exchanges, where each conditional write exchange writes a 32 bit value from a data register to a location in data share… |
| ds_consume | ds_consume | DS | Subtract (count_bits(exec_mask)) from the value stored in DS memory at (M0.base + instr_offset) if GDS, or at instr_offset if LDS. |
| ds_dec_rtn_u32 | ds_dec_rtn_u32 | DS | Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… |
| ds_dec_rtn_u64 | ds_dec_rtn_u64 | DS | Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… |
| ds_dec_src2_u32 | ds_dec_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_dec_src2_u64 | ds_dec_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_dec_u32 | ds_dec_u32 | DS | Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… |
| ds_dec_u64 | ds_dec_u64 | DS | Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a… |
| ds_gws_barrier | ds_gws_barrier | DS | GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied. |
| ds_gws_init | ds_gws_init | DS | GDS Only: Initialize a barrier or semaphore resource. |
| ds_gws_sema_br | ds_gws_sema_br | DS | GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a… |
| ds_gws_sema_p | ds_gws_sema_p | DS | GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the… |
| ds_gws_sema_release_all | ds_gws_sema_release_all | DS | GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore. |
| ds_gws_sema_v | ds_gws_sema_v | DS | GDS Only: The GWS resource indicated processes this opcode by updating the counter and labeling the resource as a semaphore. |
| ds_inc_rtn_u32 | ds_inc_rtn_u32 | DS | Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. |
| ds_inc_rtn_u64 | ds_inc_rtn_u64 | DS | Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. |
| ds_inc_src2_u32 | ds_inc_src2_u32 | DS | AMDGPU DS vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_inc_src2_u64 | ds_inc_src2_u64 | DS | AMDGPU DS vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_inc_u32 | ds_inc_u32 | DS | Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. |
| ds_inc_u64 | ds_inc_u64 | DS | Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. |
| ds_load_2addr_b32 | ds_load_2addr_b32 | DS | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… |
| ds_load_2addr_b64 | ds_load_2addr_b64 | DS | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… |
| ds_load_2addr_stride64_b32 | ds_load_2addr_stride64_b32 | DS | Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a… |
| ds_load_2addr_stride64_b64 | ds_load_2addr_stride64_b64 | DS | Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a… |
| ds_load_addtid_b32 | ds_load_addtid_b32 | DS | Load 32 bits of data from a data share into a vector register. |
| ds_load_b128 | ds_load_b128 | DS | Load 128 bits of data from a data share into a vector register. |
| ds_load_b32 | ds_load_b32 | DS | Load 32 bits of data from a data share into a vector register. |
| ds_load_b64 | ds_load_b64 | DS | Load 64 bits of data from a data share into a vector register. |
| ds_load_b96 | ds_load_b96 | DS | Load 96 bits of data from a data share into a vector register. |
| ds_load_i16 | ds_load_i16 | DS | Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. |
| ds_load_i8 | ds_load_i8 | DS | Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. |
| ds_load_i8_d16 | ds_load_i8_d16 | DS | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register. |
| ds_load_i8_d16_hi | ds_load_i8_d16_hi | DS | Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register. |
| ds_load_tr16_b128 | ds_load_tr16_b128 | DS | AMDGPU DS vector instruction operating on b128 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_load_tr4_b64 | ds_load_tr4_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_load_tr6_b96 | ds_load_tr6_b96 | DS | AMDGPU DS vector instruction operating on b96 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_load_tr8_b64 | ds_load_tr8_b64 | DS | AMDGPU DS vector instruction operating on b64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_load_u16 | ds_load_u16 | DS | Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. |
| ds_load_u16_d16 | ds_load_u16_d16 | DS | Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register. |
| ds_load_u16_d16_hi | ds_load_u16_d16_hi | DS | Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register. |
| ds_load_u8 | ds_load_u8 | DS | Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. |
| ds_load_u8_d16 | ds_load_u8_d16 | DS | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register. |
| ds_load_u8_d16_hi | ds_load_u8_d16_hi | DS | Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register. |
| ds_max_f32 | ds_max_f32 | DS | Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_f64 | ds_max_f64 | DS | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_i32 | ds_max_i32 | DS | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_i64 | ds_max_i64 | DS | Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_num_f32 | ds_max_num_f32 | DS | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_num_f64 | ds_max_num_f64 | DS | Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_num_rtn_f32 | ds_max_num_rtn_f32 | DS | Select the IEEE maximumNumber() of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_num_rtn_f64 | ds_max_num_rtn_f64 | DS | Select the IEEE maximumNumber() of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_f32 | ds_max_rtn_f32 | DS | Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_f64 | ds_max_rtn_f64 | DS | Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_i32 | ds_max_rtn_i32 | DS | Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_i64 | ds_max_rtn_i64 | DS | Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_u32 | ds_max_rtn_u32 | DS | Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_rtn_u64 | ds_max_rtn_u64 | DS | Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. |
| ds_max_src2_f32 | ds_max_src2_f32 | DS | AMDGPU DS vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
| ds_max_src2_f64 | ds_max_src2_f64 | DS | AMDGPU DS vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |