ds_load_2addr_stride64_b64 GPU Native ISA AMD Vector

LDS / Data Share

ds_load_2addr_stride64_b64

Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…

Also written as ds_read2st64_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
01111000
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 120 in OP rebuilds 0x00000000D9E00000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (encoding ENC_DS, field layout), AMD RDNA 3 (encoding ENC_DS, field layout). The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 120
Identifier 0x00000000D9E00000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64 bits of arbitrary data. Packed 2-component value. (OPR_VGPR, FMT_NUM_PK2_B64)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

Example

ds_load_2addr_stride64_b64 v[5:8], v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources