ds_gws_barrier GPU Native ISA AMD Vector

LDS / Data Share

ds_gws_barrier

GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied.

Encoding

Binary Layout (AMD CDNA 3)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
10011101
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 3). Opcode 157 in OP rebuilds 0x00000000D93A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 3.5 (opcode 29, field layout), AMD RDNA 3 (opcode 29, field layout), AMD RDNA 2 (opcode 29, field layout), AMD RDNA 1 (opcode 29, field layout). The same in AMD CDNA 2.

Format DS
Width 64 bits
Opcode 157
Identifier 0x00000000D93A0000

Operands

  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 3).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied. The number of waves needed is passed in as DATA of first valid thread.

Semantics

//Determine the GWS resource to work on rid[5:0] = gds_base[5:0] + OFFSET0[5:0]; index = find first valid (vector mask); value = DATA[thread: index]; // Input Decision Machine state.type[rid] = BARRIER; if(state[rid].counter <= 0) then thread[rid].flag = state[rid].flag; ENQUEUE; state[rid].flag = !state.flag; state[rid].counter = value; return rd_done; else state[rid].counter -= 1; thread.flag = state[rid].flag; ENQUEUE; endif. Since the waves deliver the count for the next barrier, this function can have a different size barrier for each occurrence. // Release Machine if(state.type == BARRIER) then if(state.flag != thread.flag) then return rd_done; endif; endif. CAUTION: The VGPR operand MUST be even-aligned for this instruction. Only 32 bits are used but hardware treats this instruction as a 64 bit read.

Example

ds_gws_barrier v1 gds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources