ds_cmpstore_f32 GPU Native ISA AMD Vector
DS CMPSTORE F32 LDS / Data Share
ds_cmpstore_f32
Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.
Example
ds_cmpstore_f32 v1, v2, v3A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project