ds_cond_sub_rtn_u32 GPU Native ISA AMD Vector

LDS / Data Share

ds_cond_sub_rtn_u32

Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to…

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
10101000
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 168 in OP rebuilds 0x00000000DAA00000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 168
Identifier 0x00000000DAA00000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Subtract an unsigned 32-bit integer value in the data register from a location in a data share only if the memory value is greater than or equal to the data register value. Store the original value from data share into a vector register.

Example

ds_cond_sub_rtn_u32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_ds.s). Not from an AMD document, and not authored here.

Sources