ds_bvh_stack_rtn_b32 GPU Native ISA AMD Vector

DS BVH STACK RTN B32 LDS / Data Share

ds_bvh_stack_rtn_b32

Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Ray tracing involves traversing a BVH which is a kind of tree where nodes have up to 4 children. Each shader thread processes one child at a time, and overflow nodes are stored temporarily in LDS using a stack. This instruction supports pushing/popping the stack to reduce the number of VALU instructions required per traversal and reduce VMEM bandwidth requirements.

Example

ds_bvh_stack_rtn_b32 v255, v254, v253, v[249:252]

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources