ds_add_rtn_f32 GPU Native ISA AMD Vector

LDS / Data Share

ds_add_rtn_f32

Add two single-precision float values stored in the data register and a location in a data share.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
01111001
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 121 in OP rebuilds 0x00000000D9E40000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_DS, opcode 53, field layout), AMD CDNA 3 (encoding ENC_DS, opcode 53, field layout), AMD CDNA 2 (encoding ENC_DS, opcode 53, field layout), AMD CDNA 1 (encoding ENC_DS, opcode 53, field layout), AMD RDNA 3.5 (encoding ENC_DS, field layout), AMD RDNA 3 (encoding ENC_DS, field layout), AMD RDNA 2 (encoding ENC_DS, opcode 85, field layout), AMD RDNA 1 (encoding ENC_DS, opcode 85, field layout). The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 121
Identifier 0x00000000D9E40000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Floating-point addition handles NAN/INF/denorm.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Add two single-precision float values stored in the data register and a location in a data share. Store the original value from data share into a vector register.

Semantics

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); tmp = MEM[addr].f32; MEM[addr].f32 += DATA.f32; RETURN_DATA.f32 = tmp

Example

ds_add_rtn_f32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources