ds_cmpst_rtn_f32 GPU Native ISA AMD Vector

LDS / Data Share

ds_cmpst_rtn_f32

Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value…

Also written as ds_cmpstore_rtn_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
00110001
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 49 in OP rebuilds 0x00000000D8620000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD CDNA 3, AMD CDNA 2.

Format DS
Width 64 bits
Opcode 49
Identifier 0x00000000D8620000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_F32)
  • ADDR
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_F32)
  • DATA1
    Read. N/A Data format: N/A (OPR_VGPR_OR_ACCVGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_DS encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Caution, the order of src and cmp are the opposite of the BUFFER_ATOMIC_CMPSWAP opcode.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal.

Semantics

addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32); tmp = MEM[addr].f32; src = DATA2.f32; cmp = DATA.f32; MEM[addr].f32 = tmp == cmp ? src : tmp; RETURN_DATA.f32 = tmp

Example

ds_cmpst_rtn_f32 v5, v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_ds.s). Not from an AMD document, and not authored here.

Sources