ds_bpermute_fi_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_bpermute_fi_b32

Backward permute and fetch data for invalid lanes.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
11001101
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 205 in OP rebuilds 0x00000000DB340000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 205
Identifier 0x00000000DB340000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Backward permute and fetch data for invalid lanes. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS hardware to implement an arbitrary swizzle across threads in a wavefront.

Example

ds_bpermute_fi_b32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx12_asm_ds.s). Not from an AMD document, and not authored here.

Sources