ds_bpermute_b32 GPU Native ISA AMD Vector

LDS / Data Share

ds_bpermute_b32

Backward permute.

Encoding

Binary Layout (AMD CDNA 5)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
10110011
25:18
unassigned
17:16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_VDS layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 179 in OP rebuilds 0x00000000DACC0000, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (encoding ENC_DS, opcode 63, field layout), AMD CDNA 3 (encoding ENC_DS, opcode 63, field layout), AMD CDNA 2 (encoding ENC_DS, opcode 63, field layout), AMD CDNA 1 (encoding ENC_DS, opcode 63, field layout), AMD RDNA 3.5 (encoding ENC_DS, field layout), AMD RDNA 3 (encoding ENC_DS, field layout), AMD RDNA 2 (encoding ENC_DS, field layout), AMD RDNA 1 (encoding ENC_DS, field layout). The same in AMD RDNA 4.

Format DS
Width 64 bits
Opcode 179
Identifier 0x00000000DACC0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • ADDR
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • DATA0
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VDS encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Examples (simplified 4-thread wavefronts): VGPR[SRC0] = { A, B, C, D } VGPR[ADDR] = { 0, 0, 12, 4 } EXEC = 0xF, OFFSET = 0 VGPR[VDST] = { A, A, D, B } VGPR[SRC0] = { A, B, C, D } VGPR[ADDR] = { 0, 0, 12, 4 } EXEC = 0xA, OFFSET = 0 VGPR[VDST] = { -, 0, -, B }

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Backward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS hardware to implement an arbitrary swizzle across threads in a wavefront. Note the address passed in is the thread ID multiplied by 4. Note that EXEC mask is applied to both VGPR read and write. If src_lane selects a disabled thread then zero is returned. See also DS_PERMUTE_B32.

Semantics

// VGPR[laneId][index] is the VGPR RAM // VDST, ADDR and DATA0 are from the microcode DS encoding declare tmp : 32'B[64]; declare OFFSET : 16'U; declare DATA0 : 32'U; declare VDST : 32'U; for i in 0 : 63 do tmp[i] = 0x0 endfor; for i in 0 : 63 do // ADDR needs to be divided by 4. // High-order bits are ignored. src_lane = (VGPR[i][ADDR].u32 + OFFSET.u32) / 4U % 64U; // EXEC is applied to the source VGPR reads. if EXEC[src_lane].u1 then tmp[i] = VGPR[src_lane][DATA0] endif endfor; // Copy data into destination VGPRs. Some source // data may be broadcast to multiple lanes. for i in 0 : 63 do if EXEC[i].u1 then VGPR[i][VDST] = tmp[i] endif endfor

Example

ds_bpermute_b32 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources