ds_gws_sema_release_all GPU Native ISA AMD Vector

LDS / Data Share

ds_gws_sema_release_all

GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore.

Encoding

Binary Layout (AMD CDNA 3)
VDST
63:56
DATA1
55:48
DATA0
47:40
ADDR
39:32
110110
31:26
ACC
25
10011000
24:17
GDS
16
OFFSET1
15:8
OFFSET0
7:0
 

The ENC_DS layout from AMD's machine-readable ISA specification (AMD CDNA 3). Opcode 152 in OP rebuilds 0x00000000D9300000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 1 (field layout), AMD RDNA 3.5 (opcode 24, field layout), AMD RDNA 3 (opcode 24, field layout), AMD RDNA 2 (opcode 24, field layout), AMD RDNA 1 (opcode 24, field layout). The same in AMD CDNA 2.

Format DS
Width 64 bits
Opcode 152
Identifier 0x00000000D9300000

Operands

  • 1: modifier
    Assembler modifier or optional field rather than a register. Written gds in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Semantics

// Determine the GWS resource to work on rid[5:0] = gds_base[5:0] + offset0[5:0]; // Incr the state counter of the resource state.counter[rid] = state.wave_in_queue; state.type = SEMAPHORE; return rd_done; //release calling wave This action releases ALL queued waves; it has no effect if no waves are present.

Example

ds_gws_sema_release_all gds

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources