ds_read2st64_b64 GPU Native ISA AMD Vector

DS READ2ST64 B64 LDS / Data Share

ds_read2st64_b64

Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (DS) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format DS
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in LDS / Data Share

Reference

AMDGPU / GFX ISA

Description

Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address.

Semantics

addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 512U].b32; RETURN_DATA[63 : 32] = MEM[addr + OFFSET0.u32 * 512U + 4U].b32; addr = CalcDsAddr(ADDR.b32, 0x0, 0x0); RETURN_DATA[95 : 64] = MEM[addr + OFFSET1.u32 * 512U].b32; RETURN_DATA[127 : 96] = MEM[addr + OFFSET1.u32 * 512U + 4U].b32

Example

ds_read2st64_b64 v[5:8], v1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources