ds_read2_b32 GPU Native ISA AMD Vector
DS READ2 B32 LDS / Data Share
ds_read2_b32
Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register.
Semantics
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[31 : 0] = MEM[addr + OFFSET0.u32 * 4U].b32;
addr = CalcDsAddr(ADDR.b32, 0x0, 0x0);
RETURN_DATA[63 : 32] = MEM[addr + OFFSET1.u32 * 4U].b32
Example
ds_read2_b32 v[5:6], v1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 432. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project