ds_min_u64 GPU Native ISA AMD Vector
DS MIN U64 LDS / Data Share
ds_min_u64
Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (DS)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in LDS / Data Share
Reference
AMDGPU / GFX ISA
Description
Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Update the data share with the selected value.
Semantics
addr = CalcDsAddr(ADDR.b32, OFFSET0.b32, OFFSET1.b32);
tmp = MEM[addr].u64;
src = DATA.u64;
MEM[addr].u64 = src < tmp ? src : tmp;
RETURN_DATA.u64 = tmp
Example
ds_min_u64 v1, v[2:3]A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 439. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project